Leo

fpgacapZero. fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

hdldiagZero. An agent skill that turns an HDL / RTL / SoC architecture description into a clean SVG block diagram

fresca. Versatile multi-sensor temperature controller

mjpegZero. Open source synthesizable MJPEG encoder written in behavioral RTL with AXI interfaces, up to 1080p30 on low end AMD/Xilinx 7-Series FPGAs

fpgaZeroMCP. An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed by GitHub.

axiZero. Open source AXI4 / AXI4-Lite interconnect generator. Describe your bus topology in YAML, get you Verilog back

emacZero. Open-source Ethernet MAC with AXI4-Stream, AXI4-Lite CSR, MDIO, MII to RGMII support, jumbo frames, and stats.

translateHDL. Python

serv. SERV - The SErial RISC-V CPU

vtpgZero. A synthesizable Verilog video test pattern generator IP core. Outputs pixels over an AXI4-Stream master interface and is configured at runtime via an AXI4-Lite slave register interface.

spacewire_reloaded. Open source enhanced version of spacewire core based on spacewire_light