lakshmi-sathi

avsdpll_1v8. 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Evaluation-of-NVIDIAs-Camera-to-Robot-Pose-Estimation-Deep-Learning-Research. Evaluation of the Single-Image Camera-to-Robot Pose Estimation deep learning research by NVIDIA on the Jaco Gen 2 6DoF KG-3 Robot Arm from Kinova Robotics.

caravel_avsdpll1v8. PLL IP on Caravel with OpAmps

Analog-Neural-Network. Verilog

avsdpll1v8_caravel. PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC

rosvino. A ROS package for offloading inference to the Intel Movidius VPU Neural Compute Stick. Also, Evaluation of the Intel Movidius VPU Neural Compute Stick for Real-Time Inference.

Logic_Simulator. A simple python-based logic simulator for digital logic circuits. Input the digital circuit in the standard text file form and provide the input vector to generate the corresponding output of the logic circuit.

mri_reconstruction. MRI Reconstruction. Methodology to score effectiveness of loss metrics. Incorporation of Edge Loss for boosting edges in reconstruction.

CERN-Evaluation-Task. Solution to Evaluation task from CERN

covid-detection. Python

bsg_fakeram. fakeram generator for use by researchers who do not have access to commercial ram generators

OpenROAD-flow-scripts. Verilog

FPGA_ECE8893. C++

autoencoder-latent-space-visualization. 2-dimensional visualization of the latent space learned by a deep autoencoder on MNIST