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avsdpll_1v8.
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
github.com/lakshmi-sathi/avsdpll_1v8
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@lakshmi-sathi
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