stnolting

neorv32. 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

neoTRNG. 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

neo430. :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

fpga_puf. :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

riscv-gcc-prebuilt. 📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

captouch. 👇 Add capacitive touch buttons to any FPGA!

neorv32-verilog. ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

neorv32-setups. 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

neorv32-riscof. ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

fpga_torture. 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

riscv-debug-dtm. 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

cjtag_bridge. 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.

wb_spi_bridge. 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

neorv32-freertos. 💾 FreeRTOS port for the NEORV32 RISC-V Processor.

neorv32-formal. Formal verification (experiments) targeting the NEORV32 RISC-V processor.

74xx_discrete_clock. A retro-style digital clock based on 74xx discrete logic chips

neorv32-micropython. 🐍 Port of MicroPython for the NEORV32 RISC-V Processor.

icarus-verilog-prebuilt. 📦 Prebuilt Icarus Verilog simulator package for x64 Linux.

neorv32-riscv-act. NEORV32 port of the RISC-V Architectural Certification Tests (ACTs)

vhpi_jtag. Connect to your GHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> vhpi_jtag <-VHPI-> GHDL

neorv32_soc. Playing around with the [`neorv32`](https://github.com/stnolting/neorv32) SoC on a [Gecko4Education](https://gecko-wiki.ti.bfh.ch/gecko4education:start) Board with an Intel Cyclone IV E FPGA.

riscv-arch-test. Assembly

neorv32-vunit. 🔍 Simulating the NEORV32 RISC-V Processor using the VUnit testing framework.

riscv_act. RV ACT playground