ultraembedded

riscv. RISC-V CPU Core (RV32IM)

biriscv. 32-bit Superscalar RISC-V CPU

cores. Various HDL (Verilog) IP Cores

core_ddr3_controller. A DDR3 memory controller in Verilog for various FPGAs

FPGAmp. 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

core_jpeg. High throughput JPEG decoder in Verilog for FPGA

riscv_soc. Basic RISC-V Test SoC

openlogicbit. Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

exactstep. Instruction set simulator for RISC-V, MIPS and ARM-v6m

libhelix-mp3. Fixed-point MP3 decoder (RISC-V port)

core_sdram_axi4. SDRAM controller with AXI4 interface

core_audio. Audio controller (I2S, SPDIF, DAC)

core_ft60x_axi. FTDI FT600 SuperSpeed USB3.0 to AXI bus master

core_usb_host. Basic USB 1.1 Host Controller for small FPGAs

core_usb_cdc. Basic USB-CDC device core (Verilog)

core_dvi_framebuffer. Minimal DVI / HDMI Framebuffer

fat_io_lib. Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.

core_dbg_bridge. UART -> AXI Bridge

core_soc. Basic Peripheral SoC (SPI, GPIO, Timer, UART)

core_uriscv. Another tiny RISC-V implementation

usb_sniffer. High Speed USB 2.0 capture device based on miniSpartan6+

usb2sniffer. USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

core_axi_cache. 128KB AXI cache (32-bit in, 256-bit out)

riscv-linux-boot. Trivial RISC-V Linux binary bootloader

core_spiflash. SPI-Flash XIP Interface (Verilog)

core_usb_fs_phy. USB Full Speed PHY

core_usb_uart. USB serial device (CDC-ACM)

core_usb_bridge. USB -> AXI Debug Bridge

core_jpeg_decoder. HW JPEG decoder wrapper with AXI-4 DMA

core_enet. Ethernet MAC 10/100 Mbps

core_ulpi_wrapper. ULPI Link Wrapper (USB Phy Interface)

riscv32_linux_from_scratch. RISC-V 32-bit Linux From Scratch

core_ftdi_bridge. FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

fpga_test_soc. A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

riscv_sbc. A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

minispartan6-audio. miniSpartan6+ (Spartan6) FPGA based MP3 Player

core_usb_sniffer. USB capture IP

core_mmc. MMC (and derivative standards) host controller

cortex_m0_wrapper. Cortex-M0 DesignStart Wrapper

core_ram_tester. AXI-4 RAM Tester Component

armv6m-sim. Simple instruction set simulator for ARMv6-M (Cortex M0)

librtos. Very basic real time operating system for embedded systems...

minispartan6. Projects for the Scarab Minispartan6+ FPGA board

ecpix-5. Projects for the ECPiX-5 - a ECP5 FPGA board.

altor32. AltOr32 - Alternative Lightweight OpenRisc CPU

core_mpx. MPX is a open-source CPU which can execute code compiled for MIPS-I ISA

legacy_jpeg_decoder. Verilog

ecpix5-test. Test code / bitstreams for the LambdaConcept ECPIX-5 FPGA board

xc6_bus_pirate. XC6 Bus Pirate (FPGA based multi-tool)

orangecrab. Test projects for the OrangeCrab ECP5 FPGA board

libsigrok. Read-only mirror of the official repo at git://sigrok.org/libsigrok. Pull requests welcome. Please file bugreports at sigrok.org/bugzilla.

riscv-cores-list. RISC-V Cores, SoC platforms and SoCs

rp2040_blinky. Simple blinky example for the RP2040 that does not require cmake

ps1-tests. Collection of PlayStation 1 tests for emulator development

busybox. BusyBox mirror

opensbi. RISC-V Open Source Supervisor Binary Interface

xchange. Change part number or package in a Xilinx 7-series FPGA bitstream

u-boot. "Das U-Boot" Source Tree

riscv-gcc. gcc+newlib and gcc+glibc toolchains