Tommy Thorn

Reduceron. FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

yarvi. Yet Another RISC-V Implementation

fpgammix. Partial implementation of Knuth's MMIX processor (FPGA softcore)

yari. YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.

Paperlike-Raspberry-Pi-4. How to use a Dasung Paperlike HD-F, HD-FT, and Paperlike 253 with Raspberry Pi 4 [and other hosts?]

spleentt-5x8-font. Tiny 5x8 bitmap font based on spleen and creep, useful for low-resolution displays

tinytapeout-4-bit-cpu. A design for TinyTapeout

AliExpressXCKU5P. Collateral for an AliExpress XCKU5P dev board

rk-xcku5p-f-v1.2. Collateral for the RK-XCKU5P-F V1.2 FPGA development board

virtual-nascom. SDL-based Nascom 2 emulator

simmerv. Feature-rich RISC-V RVA22 SoC emulator; runs Ubuntu etc. and more

BeMicro-CV. A "hello world" style designs for the Cyclone V based $49 Arrow BeMicro CV

verilator-demo. A very simple example of how to use Verilator

no-time-for-squares. VGA Clock Design For Tiny Tapeout 05

multisim. MultiSim is Yet Another CPU Simulator which purpose in life is to allow easy experimentation with various implementation strategies, such as superscalar in-order, sscalar out-of-order, speculative sscalar out-of-order, etc.

NCL-examples. A collection of Null Convention Logic examples, simulated and synthesized for FPGA

tt08-maxbw. An experimental asynchronous sequential multiplier

expjit3. Proof of concept dynamic code generation

tinyc-in-rust. Marc Feeley's Tiny-C compiler, rewritten in Rust

BeMicroCV-A9-case. 3D printed case for the BeMicroCV-A9 FPGA development board

dirac-spec-errata. Bug-fixed version of the official specification of the Dirac wavelet based video codec

OrangeCrab_Hello. Simple OrangeCrab Verilog design using LED and serial IO

kbe. Python

c4. C in four functions

terminal-simulator. Simulation of VT52 and VT100 terminal hardware.

tt09-tommythorn-cgates. Test structures to verify two different ways to make c-gates and rings from them

tt09-something-great. It’ll be something and it’ll be great

sta_basics_course. Introductory course into static timing analysis (STA).

ttihp-tommythorn-async-mult. Bundled-data asynchronous multiplier example

tt09-tommythorn-workshop. Quick Workshop hack: a PDM driven my inputs from a serial UART; b+1 is echoed back

ttihp-no-time-for-squares. Verilog

tt09-sram. Just experimenting with alternative SRAM implementations

bemicro_cva9_jtaguart. Small example design for BeMicro CV-A9 using JTAGUART and LEDs

formal_timer. Verilog

boom-template. A template for building new projects/platforms using the BOOM core.

kinesis-firmware. humble hacker firmware

0toasic. Stuff I did for Matt Venn's Zero-to-ASIC course

tt06-ncl-lfsr. NCL LFSR

tt06-tommythorn-4b-cpu. Silly 4b CPU v2

gdb-duel. DUEL - A high level language for debugging C programs (by Michael Golan)

homekit. Monorepo for all homekit related development, including integrated firmware, PCBs, and bridges

riscv-isa-manual. RISC-V Instruction Set Manual

kintex-7-stlv7325t-board-files.

NCL_sandbox. Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determined design in a familiar context. The tools used are Icarus verilog and gtkwave.

yarvi3. Slice

verilog-sim-bench. Verilog simulation workload extracted from Reduceron

bp. Fun with branch predictors

lisp. A version of John McCarthy's tiny Lisp (in C) with added CDR-coding

compiler. The adventures of a Haskell compiler

tt07-more-ncl-experiments. More simple NCL circuits

tt08-experiments. For now, just some experiments

bounded-spsc-queue. A Bounded SPSC queue for Rust

tt07-memory. A very crazy attempt at creating memory from a22o gates (smaller than latches)

jsnascom. Nascom 2 emulator in the browser