Martin Schoeberl

chisel-book. Digital Design with Chisel

chisel-examples. Chisel examples and code snippets

chisel-lab. Lab exercises for Chisel in the digital electronics 2 course at DTU

lipsi. Lipsi: Probably the Smallest Processor in the World

wildcat. An implementation of RISC-V

cae-lab. Lab Material for CAE

chisel-empty. An almost empty chisel project as a starting point for hardware design

risc-v-lab. Lab material for the three week course on builiding a RISC-V microprocessor

agile-hw. Agile Hardware Design Course

comphdl. Compare HDLs

tt06-chisel-template. Submission template for Tiny Tapeout 06 - Chisel HDL Projects

soundbytes. Sound effects and music related hardware (in Chisel)

tt10-wildcat. The Wildcat RISC-V

chisel-playground. Some playground for Chisel experiments

fpga-stuff. Small scribbles for FPGA that don't fit anywhere else

chisel2-doc. Have the Chisel 2.2 doc available

async-chisel. Explore asynchronous design witih Chisel

OpenSoCFabric. OpenSoC Fabric - A Network-On-Chip Generator

chip-design. Collect info for open-source chip and FPGA design

chisel. Chisel: A Modern Hardware Design Language

HPStandard. Yet Another MIPS Processor

lemberg. Lemberg is a time-predictable VLIW processor optimized for performance.

one-way-shared-memory. C

nn-chisel. Neural networks in Chisel

chisel4. Scala

tt06-chisel-vga. Tcl

VelonaCore. A VHDL implementation of a single-cycle Leros core

tt09-sigma-delta. Verilog

doppio. Doppio: Open-Source Verification with Java and Scala

tt04-chisel-demo. Chisel Demo

spi. SPI master and peripheral

tt09-experiments. Can we do some memory?

cae-examples. RISC-V assembler examples for CAE

Reduceron. FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

yarvi. Yet Another RISC-V Implementation

riscv-tools. RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

demos-ekvb. DEMoS Manifesto

yari. YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.