Olof Kindgren

serv. SERV - The SErial RISC-V CPU

1.8k

fusesoc. Package manager and build abstraction tool for FPGA/ASIC development

1.4k

edalize. An abstraction library for interfacing EDA tools

777

corescore. CoreScore

177

ipyxact. Python-based IP-XACT parser and utilities

144

vidbo. Virtual Development Board

64

fifo. Generic FIFO implementation with optional FWFT

61

subservient. Small SERV-based SoC primarily for OpenMPW tapeout

52

observer. Verilog

46

wb_intercon. Wishbone interconnect utilities

45

qerv. Verilog

21

fusesocotb. Quick'n'dirty FuseSoC+cocotb example

20

i2c. I2C controller core

16

simple_spi. SPI core

14

underserved. Verilog

11

verilatio. A protocol for communicating with HDL simulations over websockets

10

wb_bfm. Wishbone Bus Functional Model

9

de0_nano. Verilog

9

spi_ram_loader. SPI RAM loader

7

another_serv. SERV running Another World under Verilator

5

ipxact_gen. Python

4

or1k-ipxact. IP-Xact files for OpenRISC-based systems

4

wb_streamer. Wishbone component for converting data streams to wishbone transactions

3

opentitan. OpenTitan: Open source silicon root of trust

3

TinyFPGA-Bootloader. An open source USB bootloader for FPGAs

3

pdklite. Verilog

2

libstorage. Library of RTL components for data storage

2

de0_nano_ipxact. Verilog

2

reset_test. Reset demo for blog post

2

fusesoc_vunit_demo. Demo project for FuseSoC + VUnit integration

2

stream_utils. Utility functions for data streams

2

ca_workshop_munich. Material for the CHIPS Alliance workshop in Munich

2

tt08-vga-drop. "The Drop" ASIC 640x480 60Hz audio visual demo

2

libaxis. Library of RTL components for AXI Stream infrastructure

1

fewsoc.

1

or1k_bootloaders. OpenRISC 1000-compatible bootloaders

1

riscv-formal. RISC-V Formal Verification Framework

1