Morten Borup Petersen

Ripes. A graphical processor simulator and assembly editor for the RISC-V ISA

VSRTL. Visual Simulation of Register Transfer Logic

NetCracker. NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between switchboxes

mlir-interactive. Qt based UI for visual and interactive composition and execution of MLIR compilation flows.

VelonaCore. A VHDL implementation of a single-cycle Leros core

RTOC. a Real-Time Object Classifier

QtWasmThreaded. Prebuilt version of the latest Qt for WebAssembly, with thread support enabled

LLMAnki. Webapp for improving your Anki decks, using LLMs.

VelonaMP. Scala

Troeffelheltene. Trøffelheltenes opskriftseventyr