Matt Venn

awesome-opensource-asic-resources.

basic-ecp5-pcb. Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

teensy-audio-fx. Playable effects modeled on the Teenage Engineering Pocket operator series. Featuring Teensy 4 for audio processing.

first-fpga-pcb. FPGA dev board based on Lattice iCE40 8k

fpga-sdft. sliding DFT for FPGA, targetting Lattice ICE40 1k

cad. cad files for cnc machining

vga-clock. Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

wokwi-verilog-gds-test. Verilog

flipflop_demo. Flip flop setup, hold & metastability explorer tool

multi_project_tools. tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles

gtkwave-python-filter-process. Python

ws2812-core. verilog core for ws2812 leds

TinyFPGA-BX. AGS Script

vga_clock_pcb. Open source hardware down to the chip level!

librelane_summary. Python

fpga-sram. mystorm sram test

magic-inverter. an inverter drawn in magic with makefile to simulate

minim-reader. reading a british gas branded minim energy meter with a webcam and python

understanding-tinyfpga-bootloader. understanding the tinyfpga bootloader

fpga-virtual-graf. Verilog

logLUTs. Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.

crap-o-scope. crap-o-scope scope implementation for icestick

logo-to-gds2. Python

wishbone_buttons_leds. simple wishbone client to read buttons and write leds

it8512. itech it8512 python library

efabless_project_tool. Tool to fetch and parse data about Efabless MPW projects

zero_to_asic_mpw4. Verilog

simulate-gate. Project 1.1 Simulate a Skywater 130nm standard cell using ngspice

kicad. Python

pyfda-cocotb-demo. Audio filtering with pyfda and cocotb

animateVCD. animate an SVG with a VCD file

xor_vga_fpga. playing with XOR video patterns on an FPGA

fiducial. opencv python fiducial demo

simple-brushless. a cheap and simple educational brushless motor

instrumented_adder. Instrumenting adders to measure speed

caravel_user_project. Zero to ASIC group submission for MPW2

fpga-fft. Verilog

eagle-circuit-designs. nesC

frequency_counter. Project 2.2 Frequency counter

zero-to-asic-www. HTML

arduinosketchbook. all my arduino sketches

spi_client. SPI client core in verilog, tested with raspberry pi SPI master

zero_to_asic_mpw5. Verilog

fpga-dvid-ice. Verilog

klayout_properties. Ruby

litho-light. An illuminated desk stand for a 150mm photolithography mask

intro-formal-videos-resources. resources for the Introduction to Formal Verification series of videos

gate_level_simulation. Verilog

wrapped_rgb_mixer. Demo project for the Zero to ASIC Course.

formal-intro-course. materials for Formal Verification introduction course

tt08-analog-ring-osc. Tcl

seven_segment_seconds. Demo project for Zero to ASIC course & presentations

zero_to_asic_mpw7. Verilog