Efficient AI | Ph.D student @ VLSI Lab, SNU
SLEB. [ICML 2024] Official Implementation of SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks
41ReasoningPathCompression. [NeurIPS 2025] Official implementation of "Reasoning Path Compression: Compressing Generation Trajectories for Efficient LLM Reasoning"
32RelayGen. Official Implementation of "RelayGen: Intra-Generation Model Switching for Efficient Reasoning"
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