Systems software engineering, ASIC design and robotics
ev3dev-lang-js. JavaScript language bindings for ev3dev
56tidl-yolov5-custom-model-demo. A walkthrough and personal notes on running YOLOv5 models with TIDL.
35tda4vm-r5f-rust. Sandbox for Rust firmware infrastructure targeting Cortex-R5 microcontrollers on the TDA4VM.
15apio-upduino-template. Opinionated starter project for the UPduino V3 with apio. Uses sv2v for SystemVerilog support.
5adafruit-win10-iot. A set of libraries to interface with various Adafruit products from Windows 10 IoT Core
4snap-ev3dev. Snap! server and control blocks for ev3dev
4pyright-ui-test-poc. A proof-of-concept demo of Pytest unit-tests which evaluate snippets under Pyright
2rov-control-system-2018. Control system implemented for the 2018 MATE underwater ROV competition.
23D-US-Data-Map. 3D US Data Map is an in-browser 3D map of the US, split by County or State, with geographies extruded and colored based on a user-chosen formula that can access US census data.
2vscode-cdecl. cdecl: Convert C/C++ gibberish to English, and back again.
2aerial-release-system. Software, schematics and design files for building a remotely-operated arduino-based release mechanism for use in dropping payloads from a suspended location.
2must-implement-trait. An attribute proc-macro which enforces that a type (auto-)implements the specified trait(s).
2blockly-ev3dev. The web-based visual programming editor.
2my-first-cpu. Archive of the first CPU core (and, generally, first significant digital logic design) I built. Published only for historical reference.
1mcl. My own toy implementation of Monte Carlo Localization for 2D laserscans.
1ev3dev-NodeJS. ev3dev API language bindings for NodeJS (written in TypeScript)
1curly-parakeet. Repro case for http://stackoverflow.com/q/34100444/2422874 and derivative bug reports
1gitlab-ci-test. C++
1combinator-quick-reference. A type-indexed cheat-sheet for Rust's Result and Option "combinators": unwrap, map, ok, etc.
1pipelined-rv32i-core. A toy RISC-V processor design implemented in SystemVerilog, targeting FPGA.
1aruw-project-otto-2022-archive. By the way, is there anyone on board who knows how to fly a plane?
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