Steve Hoover

LF-Building-a-RISC-V-CPU-Core. TL-Verilog

warp-v. WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

RISC-V_MYTH_Workshop. Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop

makerchip_examples. TL-Verilog

LF-Building-a-RISC-V-CPU-Core-Course. The Linux Foundation/Redwood EDA "Building a RISC-V CPU" Course content, also available via EdX.

conversion-to-TLV. A repository for exploring LLM-assisted code conversion to TL-Verilog.

1st-CLaaS. Developing Smith Waterman accelerators on F1 instances using 1st CLaaS

MYTH_Workshop_Assignments. Starting-point template for students in the Microprocessor for You in Thirty Hours Workshop

VSDOpen2020_TLV_RISC-V_Tutorial. For students of the VSDOpen2020 TL-Verilog RISC-V Tutorial

immutable. TL-Verilog

warp-v_includes. A companion to /warp-v containing files that are included from /warp-v.

LLM_TLV. Misc content for working with TL-Verilog, VIZ, etc. using LLMs

VSDBabySoC. VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

awesome-opensource-hardware. List of awesome open source hardware tools, generators, and reusable designs

drop4game. A four-in-a-row game for Makerchip.

Cores-SweRV. SweRV EH1 core

gian-course. GIAN Course (leveraging CC-0 content from ChipCraft)

awesome-hdl. Hardware Description Languages

SweRV_VIZ. Visualization of the SweRV core using Visual Debug within Makerchip.

risc-v-core. This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

warp-v_ci_env. Provides the environment used by warp-v continuous integration testing, which runs riscv-formal.

Pipelining-a-RISC-V-CPU.

test. hooo

vcdrom. 🇻 🇨 🇩 viewer PWA

FPGAPlayground. A repository for FPGA tinkering by the "Chip Design in Eastern MA" Meetup.com group.

educational-materials. Educational materials for RISC-V

tt05-verilog-demo. Verilog Demo, updated for Tiny Tapeout 05

ChipEXPO-2021. For participants of ChipEXPO-2021

riscv-formal. RISC-V Formal Verification Framework

tt06-tl-verilog-template. Submission template for Tiny Tapeout 06 - Verilog HDL Projects