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myrtle

Elite
@gatecat

FPGA tool dev • kbitycat of the mountains • she • 🏳️‍🌈🏳️‍⚧️🐱🦈🦈🦈

CSI2Rx. Open Source 4k CSI-2 Rx core for Xilinx FPGAs

418

nextpnr-xilinx. Experimental flows using nextpnr for Xilinx devices

260

prjoxide. Documenting Lattice's 28nm FPGA parts

153

TrellisBoard. Ultimate ECP5 development board

118

BreadboardSim. Circuit Simulator with Breadboard UI

104

hrt. Hot Reconfiguration Technology demo

42

meowality. Python

17

SNES_MiSTer_ulx3s. SNES for MiSTer

16

subprime. C++

16

litex-nexus-mipi. MIPI testing with LiteX on CrossLink-NX

14

tinytapeout-fpga-test. Verilog

13

emu293. emu293 SPG293 emulator and associated tooling

11

nextpnr-xilinx-meta. Metadata for the nextpnr-xilinx xc7 flow

10

openvtx. Emulator for VT168 etc

9

n32emu. Native32 reverse engineering and emulation project

9

fabulous-mpw2-bringup. Verilog

6

mistral-test. Verilog

6

meowality-hls. Rust

5

cxxrtl-soc-demo. Python

5

one_hot_fpga_gf180. FPGA with a custom SRAM+mux bitcell for onehot routing

3

h265-encoder-rtl. Verilog

3

nexus-dsp-hwtests. Verilog

3

pyra-kernel-devel. C

3

meowtrascale. C++

2

fabulous-tapeout-automation. Python

2

mistral. Cyclone V bitstream reverse-engineering project

2

scratching-post. Python

2

prjoxide-db. prjoxide database

2

fabulous_mpd. Example digital project for the Efabless Caravel "openframe" harness

2

litex. Build your hardware, easily!

2

vtr-verilog-to-routing. Verilog to Routing -- Open Source CAD Flow for FPGA Research

2

fabulous_mpw0gf. fabulous efpga tapeout on gf180

2

coriolis. Coriolis VLSI EDA Tool (LIP6)

1

RapidWright. Build Customized FPGA Implementations for Vivado

1

litex-fpga-interchange. Python

1

fpga-interchange-schema. Cap'n Proto

1

nextpnr. nextpnr portable FPGA place and route tool

1

OpenROAD. OpenROAD's unified application implementing an RTL-to-GDS Flow

1

open-src-cvc. Mirror of tachyon-da cvc Verilog simulator

1

tt02-melody-gen. melody generator for tt02

1

interchange-experiments. random experiments with the FPGA interchange format

1

mister_nes_gfmpw1. Verilog

1

simplaceity. attempting a VLSI port of the nextpnr SimPL+SA placer approach

1

tt02-pic. subset of a PIC processor for tinytapeout

1

python-fpga-interchange. Python interface to FPGA interchange format

1

amaranth. A refreshed Python toolbox for building complex digital hardware

1