Anderson Ignacio

ravenoc. RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

axi_dma. General Purpose AXI Direct Memory Access

nox. RISC-V Nox core

mpsoc_example. Verilog

riscv_verilator_model. RISCV model for Verilator/FPGA targets

cocotbext-ahb. Cocotb AHB Extension - AHB VIP

ahb_lite_bus. AHB Bus lite v3.0

digital_design_library. List of several designs I have been working through the years to avoid re-designing it again

iir_filter. IIR Lowpass Filter

mqtt-sn-contiki_example. Example of MQTT-SN with Contiki-OS for blog.aignacio.com

cocotbext-waves. Generate wavedrom figures out of design signals

skid_buffer. Python

jtag_axi. JTAG to AXI master

soc_components. SystemVerilog

mser. MATLAB Implementation of MSER LT algorithm

nox_freertos. C

cdc_components. Collection of different designs for clock domain crossing

ahb3lite_apb_bridge. Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

apu_cluster. This project is to be instantiated inside pulp_cluster and wraps all shared processing units.

memory. Generic memory implementations

ahb3lite_memory. Multi-Technology RAM with AHB3Lite interface

ethernet_axi. AXI wrapper around Ethernet module

deca_board_demo. Verilog

cyclonev_example. Files for "Getting Through Cyclone V" post from blog.aignacio.com

bus_arch_sv_pkg. AMBA SystemVerilog structs

esp_homestark. Fork from [ https://github.com/tuanpmt/esp_mqtt + https://github.com/tuanpmt/esp_mqtt ]

hwacha_vvadd_benchmark. Benchmark for Hwacha vector accelerator of vvadd computation tweaked

kicad-library. This repo contains KICAD libraries necessary for designing hardware projects

CycloneVSoC-examples. Examples using the Cyclone V SoC chip

opencv_extra. OpenCV extra data

mser_baremetal. Makefile

riscv-boot. Studying risc-V boot process

riscv-asm-manual. RISC-V Assembly Programmer's Manual

riscv-formal. RISC-V Formal Verification Framework

tiva_arm_template. Tools for a complete environment to develop on TIVA launchpad arm {TM4C123GH6PM}

nox_soc_test. Basic NoX SoC tests

segmentation_opencv_linux. C++ Application to segment an input image

small_riscv_qemu_program. CMake

fusesoc-cores. FuseSoC standard core library

cache_performance_model. Simple cache model to evaluate performance through different topologies

exampleSTMF32Bluepill. Example of STMF32 App for blog.aignacio.com

async_gp_fifo. Python

ahb3lite_pkg. Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces

riscv-arch-test-nox. HTML

homestark_mqtt_6lowpan_port. Porte do MQTT-SN para o Contiki

zigbee_tests. Smart sensor node Network using Z-stack from texas instruments and CC2530

verilog-ethernet. Verilog Ethernet components for FPGA implementation

riscv. RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

blinky. Example LED blinking project for your FPGA dev board of choice