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RISC-V International Open Source Laboratory

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@RIOSLaboratory

The RISC-V International Open Source Laboratory (RIOS Lab) will bring the research effort of RISC-V CPU ecosystems from UC Berkeley to the rest of the world

www.rioslab.org/

OpenRPDK28. Open source process design kit for 28nm open process

84

OpenXRAM. sram/rram/mram.. compiler

54

OpenSTDCell28. Open stadard cell library for open 28nm process

17

Open3DFlow. Jupyter Notebook

12

CyberRio-V1.0. A small RISC-V core written in synthesizable Verilog, with the majority of the Verilog code implementation done using GPT-4, that supports the RV32I unprivileged ISA and parts of the privileged ISA, namely M-mode.

5

Open3DRISCV. Verilog

4

PicoRioCPU2641300. PicoRio2 CPU MPW

3

GreenRio-V2.0. Open source RISC-V CPU

3

sail-rgen. Sail architecture definition language with RGen enhancements

3

IRAM. The new development of Berkeley IRAM project

2

3DChipTech.

2

OpenBMIChip. The OpenBMIChip is an incredible piece of silicon chip, specifically designed to support the incredibly fascinating Brain-Machine Interface (BMI).

1

GreenRio-V1.0. Open source RISC-V CPU

1

HDLGPT.

1

sail-riscv-rgen. Sail RISC-V model with RGen enhancements

1